1. Field of the Invention
The present invention relates to PCI-Express devices and more particularly, to detecting that a receiver is connected and available.
2. Background of the Invention
Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with peripheral devices via an interface such as the Peripheral Component Interconnect (“PCI”) interface, a local bus standard using parallel data transfer that was developed by Intel Corporation®, or the extension of PCI known as PCI-X. More recently, PCI-Express, a standard interface incorporating PCI transaction protocols at the logical level, but using serial data transfer at the physical level has been developed to offer better performance than PCI or PCI-X.
PCI-Express is an Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) that is compatible with existing PCI cards using the PCI Express bus. PCI-Express uses discrete logical layers to process inbound and outbound information. In the PCI-Express terminology, a serial connection between two devices is referred to as a link.
Various other standard interfaces are also used to move data between host systems and peripheral devices. Fibre Channel is one such standard. Fibre Channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols.
Host systems are used in various network applications, including storage area networks (“SANs”). In SANs, plural memory storage devices are made available to various host computing systems. Data in a SAN is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification) through various controllers/adapters, for example, host bus adapters (“HBAs”).
HBAs (a PCI-Express device) that are placed in SANs receive serial data streams (bit stream), align the serial data and then convert it into parallel data for processing, as described above. HBAs operate as a transmitting device as well as the receiving device.
PCI-Express devices (for example, HBAs' in SANs) receive serial data, align the serial data and then convert the serial data into parallel data. PCI-Express devices use PCI-Express core logic for interfacing with host systems. The PCI-Express core logic includes a control status module (“PCS module”) that has a serial/de-serializer (“SERDES”), besides other components. The SERDES in the PCS communicates with a SERDES in a host system. Before the SERDES in the PCS module can communicate with a SERDES in the host system, the PCS module detects if a receiver (i.e. the SERDES in the host system) is present and/or available to receive data.
In conventional systems, a SERDES vendor provides the mechanism to detect if a receiver is present. Often, the mechanism provided indicates that a receiver is present by using specific receiver detection protocol incorporating a set frequency, for example, 3 to 15 kilohertz if a receiver is present or above 30 kilohertz is a receiver is not present. Such proprietary conventional techniques have shortcomings. For example, detecting a receiver at a frequency of 3 kilohertz may cause delay and may take too long. Therefore, there is a need for a method and system to perform the receiver detection efficiently.